A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

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An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 μs, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 μW/channel power consumption.

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