The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, VTP and VTN. Both outputs are referenced to the same VDD supply line, and hence, the circuit can be used as a convenient test device. The VTP extractor is based on the “nested” connection of two transistors; the VTN extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The circuit was realized in 0.8 μm technology, and the results of simulation and experiment are compared. Recommendations to improve the design are given.