An electronic circuit is presented that encodes an array of analog input signals into a digital number. The digital output is a ‘rank order code’ that reflects the relative strength of the inputs, but is independent of the absolute input intensities. In that sense, the circuit performs an adaptive analog to digital conversion, adapting to the average intensity of the inputs (i.e. effectively normalizing) and adapting the quantization levels to the spread of the inputs. Thus, it can convey essential information with a minimal amount of output bits over a huge range of input signals.
As a first processing step the analog inputs are projected into the time domain, i.e. into voltage spikes. The latency of those spikes encodes the strength of the input. This conversion enables the circuit to conduct further analog processing steps by asynchronous logic.
The circuit was implemented as a prototype on a VLSI chip, fabricated in the AMS 0.6 μm process. The implementation takes 31 analog inputs that are delivered as frequency encoded spike trains by a 5 bit AER (address event representation) bus. The output is 128 bits wide and is read serially in 16-bit packages. Based on tests with one particular set of inputs with an entropy of 112.62 bits, it is estimated that the chip is able to convey 40.81 bits of information about that input set.
Possible applications can be found in speech recognition and image processing.