A Novel Architecture for Programmable Fractional-N PLL

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Abstract

In this paper, a novel architecture for programmable fractional-N PLL is proposed. Unlike the conventional fractional-N PLL, it does not need any input data word to meet step size requirement. It features programmability in step sizes. The ratio of the externally controlled counter values sets the step size and thus step size is not limited by fixed hardware. A flow chart is provided to understand the operation of the various counters used in the proposed architecture. A behavioral modeling approach is attempted to perform overall system simulation using Hspice. A 2.4 GHz fractional-N PLL prototype is demonstrated using 0.35 μm CMOS process and test results are provided. It has step sizes of the values of integer multiples of 50 kHz. The main contributions include: (i) Novel architecture, and (ii) Prototype implementation, all for programmable fractional-N PLL. Unlike the most PLLs, the proposed PLL system is amenable to behavioral system simulation using Hspice.

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