A Unitary Analysis of some Voltage and Current Mode Linear Circuits
Modeling and Characterization of the 3rd Order Charge-Pump PLL
Using High Frequency Operational Amplifiers for Low Noise Design
A Single Chip 160 Mbit/s Cable Communication Circuit Including a Gain Controlled Equalizer and a Data Regenerating PFLL
Design Strategies for Class A CMOS CCIIS
Modified Latin Hypercube Sampling Monte Carlo (MLHSMC) Estimation for Average Quality Index