Interconnect Macromodelling and Approximation of Matrix Exponent
Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages
A Wide Bandwidth Isolation Amplifier Design Using Current Conveyors
A Rank Encoder
A Square-Root Domain Differentiator Circuit
A Balanced Capacitive Threshold-Logic Gate
Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers
A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor
Novel Canonic Current Mode DDCC Based SRCO Synthesized Using a Genetic Algorithm
SITO High Output Impedance Transadmittance Filter Using FTFNs
New Wide Band Low Power CMOS Current Conveyors
A Four Quadrant Analog Multiplier Employing Single CDBA
A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits