A clock jitter error compensation and auto-tuning structure for continuous-time ΣΔ modulators

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Abstract

A novel feedback current compensation structure is proposed to suppress signal-to-noise ratio (SNR) degradation of continuous-time (CT) sigma-delta (Σδ) modulators caused by clock jitter. In order to suppress coefficients errors due to process variation, this structure can be reused to automatically tune the integration capacitor to a value with acceptable error. Both the auto-tuning function and jitter error compensation function are suitable for active-RC integrator and Gm-C integrator. This structure is implemented in a third-order single-bit CTΣδ modulator operating at sampling frequency of 200 MHz and OSR = 48. Compared with modulator without compensation, the SNR is simulated to be improved by 30 dB under a clock jitter of 2.5%. The coefficients of modulator are simulated to be tuned to the value with the error of less than 2.8% under the process variation of 70–130%.

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