Scan Test Response Compaction Combined with Diagnosis Capabilities

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As today's process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.

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