Partitioning Processor Arrays under Resource Constraints
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP
A Linear Systolic Array for Real-Time Morphological Image Processing*
Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures*
Low-Area/Power Parallel FIR Digital Filter Implementations