Guest Editors' Introduction
System-Level Power Optimization of Video Codecs on Embedded Cores
Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling
A VLSI Architecture for Separable 2-D Discrete Wavelet Transform
VLSI Array Architectures for Pyramid Vector Quantization
Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding
An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting
A Low Power DSP Engine for Wireless Communications
Low Power Digital Frequency Conversion Architectures