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A new channel decoder LSI, which will be used in digital satellite TV broadcasting Set-Top Boxes, has been designed. This LSI's functions include AD/DA conversion, QPSK demodulating, Viterbi decoding, frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) decoding, and descrambling. We use a new method for Viterbi Decoding called the Tracking Survivor State Information (TSSI) method, which not only reduces power consumption, but also solves the problem of increasing memory size. To reduce the size of RS decoder circuit, we used a three-stage-pipeline structure as well as designed a new architecture to realize Euclid's algorithm. This device has been fabricated in a 0.35 µm 3-metal CMOS standard cell-based process and is composed of 670 K transistors. In this paper, we describe the TSSI method of the Viterbi Decoder and the Reed-Solomon Decoder's new 3-stage pipeline architecture.