System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach


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Abstract

A battery powered multimedia communication device requires a very energy efficient implementation. The required efficiency can only be acquired by careful optimization at all levels of the design. System-level power optimizations have a dramatic impact on the overall power budget. We have proposed a system-level step-wise methodology to reduce the power in hardware realizations of data-dominated applications, which is partly supported with our ATOMIUM environment. In this paper, we extend the methodology to the realization of embedded software on processor cores. Starting from a high level algorithm description (e.g., in C), a set of optimizations gradually refine the code and the corresponding memory organization of the array data types. These array data types represent a fully detailed optimized data storage and transfer organization. Instead of creating the physical memories, a mapping can be done either on a general memory architecture, including a cache, or on a custom memory architecture. First, typical optimizations addressed by our methodology are applied on a didactical example. The effectiveness of this methodology is then demonstrated by the optimization of two complex applications in an embedded processor context: a MPEG2 and a H.263 video decoder. The impact of the power optimizations on the typical power consumption is demonstrated by simulating the optimized decoders with real video streams.

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