VLSI Array Architectures for Pyramid Vector Quantization


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Abstract

We present parallel algorithms and array architectures for pyramid vector quantization (PVQ) [1] for use in image coding in low-power wireless systems. PVQ presents an alternative to other quantization methods which is especially suitable for symmetric peer-to-peer communications like video-conferencing. But, both the encoding and decoding algorithms have data-dependent iteration bounds and data-dependent dependencies which prevent efficient parallelization of the algorithms for either hardware or software implementations. We perform an algorithmic transformation [2] to convert the data-dependent regular algorithms to equivalent data-independent algorithms. The resulting regular algorithms exhibit modular and regular structures with minimal control overhead; hence, they are well suited for VLSI array implementation in ASIC or FPGA technologies. Based on our parallel algorithms and systematic design methodologies [3], we develop linear array architectures. Both encoder and decoder architectures consist of L identical processors with local interconnections and provide O(L) speed-up over a sequential implementation, where L is the dimension of a vector. The architectures achieve 100% processor utilization and permit power savings through early completion. A combined encoder-decoder architecture is also presented.

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