A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints
A Low Power 8 × 8 Direct 2-D DCT Chip Design
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Constant Number Serial Pipeline Multipliers
A Hardware Architecture for the LZW Compression and Decompression Algorithms Based on Parallel Dictionaries
Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming*
A New Neuro-Fuzzy Classifier with Application to On-Line Face Detection and Recognition