Guest Editorial
A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming
Performance-Scalable Array Architectures for Modular Multiplication*
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers*
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation