Guest Editorial
QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP
Power-Aware 3D Computer Graphics Rendering
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes
Energy Efficient VLSI Architecture for Linear Turbo Equalizer
A Scalable System Architecture for High-Throughput Turbo-Decoders
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders
High Speed FPGA-Based Implementations of Delayed-LMS Filters
Optimum Downlink Power Control of a DS-CDMA System via Convex Programming
Flexible Implementation of a WCDMA Rake Receiver
Interleaving on Parallel DSP Architectures
A/D Precision Requirements for Digital Ultra-Wideband Radio Receivers