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This paper presents an ASIC implementation of a WCDMA Rake receiver targeted for mobile terminals. The implementation is based on a FlexRake architecture that shares hardware resources between multipath components and uses data-level parallelism for despreading multiple code channels. This approach facilitates the flexibility of multipath operation and improves the receiver hardware efficiency. The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells. Synthesis for 0.18 μm CMOS technology resulted in 0.238 mm2 area and 45.5 μW power consumption at 1.6 V.