A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems
A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection
Resource Sharing Combined with Layout Effects in High-Level Synthesis
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding
A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications