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This work describes the VHDL design and implementation of block-based motion estimation in order to make it feasible for real-time video applications. The design was functionally tested and simulated using ModelSim from Mentor Graphics tools, and then verified using both a VHDL testbench and the Matlab® Image processing tools. The design was tested for different image sizes at different clock frequencies with varying block sizes and search areas. With a clock frequency of 400 MHz, the estimated time for motion estimation for QCIF and CIF sequences shows the feasibility for real-time video-codec.