High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems

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We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints. Two classes of codes are considered: one, based on combinatorial objects derived from difference sets and generalizations of non-averaging sequences, and another, based on progressive edge-growth techniques. The proposed implementation reduces routing congestion, a major issue not addressed in prior work. The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. The described LDPC designs can be modified to accommodate widely different requirements, such as those arising in recording systems, as well as wireless and optical data transmission devices.

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